Autore: admin

E’ sempre interessante discutere di argomenti di alto livello tecnologico come interpretare la densità di transistor stipabili in un microchip.
Premesso che il nome attribuito ad un livello tecnologico (3nm, 7nm, 2nm) non ha più alcun collegamento con le dimensioni fisiche del dispositivo sottostante, in questo articolo di Quora si trova un’analisi abbastanza dettagliata delle prestazioni delle varie tecnologie adottate dalle principali aziende del settore (in primis TSMC, Samsung, Intel, IBM).

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Many, maybe 90% people, think 3nm represents transistor size. And they are VERY wrong!
3nm is just a name having nothing with real physical dimensions. In the past, before Intel “invented” FinFET and started using them with 22nm node in 2011, nm represented width of the MOSFET channel. But with FinFET things change and they changed in 2024 with FinFET was replaced with GAA.
Here is nice picture showing how MOSFET evolved:

With FinFET MOSFETs entered 3D world. Let me show IBM 2nm node from 2019 (experimental), electron microscope picture of a transistor:

Is above anything physical 2nm in size? NO.
Actual single transistor size was cca 50 x 70 nm. With FinFET is “worse” cause FinFET performance depends on number of fins – more fins – faster transistor.

Real measurements used are CPP (gate pitch) and MPP (metal pitch). Here table from Wiki which connects them to physical feature dimensions:

As in IBM picture above, CPP (gate pitch) for 2nm node was 48 nm.
Notice also how pitch drops a bit while node names halved, eg 3nm CPP is 48 while for 2nm is 45 nm.

TSMC was first one to introduce node names expressed in nm while Intel (and others) followed. And Intel complained for reason. Do you remember old Intel 10nm node? It was total disaster Intel struggled with but it was later renamed to Intel7 or 7nm. Why?
Cause TSMC 7nm node and Intel 10 nm had similar feature sizes. For example, TSCM 7nm CPP was 57nm while Intel 10nm was 60 nm and MPP was identical, 40 nm.

As node name represents nothing physical, Intel suggested to use SRAM cell area as measurement.
A typical SRAM cell has 6 transistors (so called 6T), having schematics like this:

On the right side is physical layout with traces connecting transistors. Looking at physical areas for different nodes we have:

7nm (Intel 10nm):

3nm:

SRAM cell size is better physical dimension but still depends on node.
Looking at TSMC 2nm and Intel18A (1.8nm), TSMC is bit smaller but Intel is faster. TSMC uses smaller transistors and maximal clocks are around 4 GHz, while Intel uses larger transistors and clocks are above 5 GHz. And, of course, Intel consumption is higher.

Another factor is kind of chip. Memories are way, way, way simpler than CPUs and higher densities are achievable. Above IBM 2nm chip was simple one.
DRAM or FLASH are not reliable for measurements, especially FLASH having hundreds of layers, 321 in 2024. DRAM uses single transistor while FLASH stores up to 4 bits into single transistor. SRAM stores single bit and is fastest. But, besides 6T, also 4T exists.

Anyway, today nm stays as node name and it will stay so for few years to come.